FPGAĿϵṇ(ϵ)FPGA̖̎OӋ |
nĿ |
ᘌAlteraĔ̖̎QMӖ˽FPGAĔ̖̎ϵywϵYϵy_lջFPGAĔ̖̎㷨OӋ{ԇCg |
༉Ҏģh |
˱CӖЧӻӭh҂ԳСnÿڈ˔35ˣˆTŵһM |
nrgnc |
ncϺͬW()/³ǽ̄(11̖y·վ) ڷֲӰB(Fһ̖Ժվ)/ڴWɽԺ ֲɽWԺ/δ Ͼֲ۴B(·) hֲԴB¶· ɶֲI^^1̖кʹ ꖷֲW/լƷ ݷֲݴW/\AB ʯfֲӱƼW/B VݷֲVZB ֲƷB
_nrg(ĩ/Bm/ࣩFPGA_rg2025818...ֱFӖԿ....ķ..............--_n--_nՈǰ... |
Wr͌WM |
nr536Wr
،WTʳޣǰA
ע|
߅v߅
ϸWTM]
ϸWTMClP̎YCIY|
ע߶Ӗ15ﺣṩCõИIďVJWT
õҵJͬܵˆλďVٝu
OՈc@鿴 |
|
Fwݴʩ95ۃ˻9ۃ ע⣺xW{WCʹһҲ500Ԫ |
| |
1Ӗ^УвփⲻãMԺӖ
2ӖYMṩļgֱ֧֣CӖЧ
3ӖϸWTM]͘IC ϸWTMClP̎YCIY|ע߶Ӗ13꣬ﺣṩCõИIďVJɣWTõҵJͬܵˆλďVٝu |
n̴V |
һA |
һAȽB̖̎ĻΌ̖̎ăɷNQMз͌ȣcvÔ̖̎ģKFPGAFͨ^ӲZԌ@ЩģKCWT㷨ӲFJRͨ^MatlabSimulinkʹ÷ĺҪBWTҪĔ̖̎ߵʹ÷[Altera]Ĕ\IPMнB` |
1.
̖̎
1.1 ̖ıʾcֻ
1.2 ıʾ
1.3 ɘԭ
1.4 ~׃Q
1.5 V
ADӿڌ}ADcFPGAӿڡ
2. ̖̎QOӋ
2.1 yDSP̎Q
2.2 FPGAĽQ
2.3 FPGA+DSPQ
DSPӿڌ}TI DSPcFPGAӿڡ
ٻ}FPGAеSERDES
3. Ô̖̎ģKFPGAF
3.1 Ӝp˳FPGAF
3.2 DDSFPGAF
3.3 FFTFPGAF
3.4 CordicFPGAF
3.5 VFPGAF |
1. MatlabcSimulinkʹÌ`
1.1 MatlabA
1.2 Mļ_c
1.3 SimulinkA
1.4 Simulinkģ
2. [Altera]е͔̖̎IPʹÌ`
2.1 VIPˣFIR
2.2 ׃QIPˣFFT
2.3 {IPˣDDS
2.4 aIPˣCORDIC8b/10b
|
ڶA |
ڵڶAΣcB[Altera
DSP Builder]PݣOӋIPģKBʹ÷SimulinkдӴλ㷨YvModelSimMЅfͬķ[SignalTap]
MܛӲf{yԇֶ |
1.
[Altera]DSPQOӋ
2. [Altera]FPGADSPYԴ
3. [DSP Builder]IP
4. [DSP Builder]
5. [DSP Builder]ܛӲf{yԇ
ͨеĔ̖̎팣}
ýw̖̎팣} |
1. [DSP Builder]ʹ÷
1.1 һ[DSP Builder]ϵy
1.2 ӴλOӋϵy
1.3 IPģKOӋҪc
2. 漰{ԇ`
2.1 DDS̖ԴOӋcModelsim
2.2 [SignalTap]{ԇ`
2.3 [DSP Builder cQuartus II]Ľӿ
DSP}_l` |
|