培訓方式以講課和實驗穿插進行。
Assura Verification
The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.
Learning Objectives
In this course you will:
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o Verify your physical IC design with Assura Verification?
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o Set up and run DRC and LVS?
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o?Locate and display results from DRC and LVS runs?
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o Run verification in various input and run modes
Audience
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o CAD Developers
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o Design Engineers
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o? Layout Designers
Prerequisites
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o Layout design experience
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o Physical verification experience
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o UNIX OS
Course Agenda
Unit 1
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o?Introduction?
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o?Using Assura Verification?
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o?Operational details?
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o?Inputs and outputs?
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o?Interactive debugging environment?
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o?DRC and LVS runs
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o?Running design-rule checks (DRC)?
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o?DRC error debugging techniques?
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o?Error Layer Window?
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o?Setting up DRC run parameters
Unit 2
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o?Running design rule checks (continued)?
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o?Antenna check?
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o?Density check
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o?Running layout versus schematic (LVS) checks?
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o?Understanding and debugging LVS check reports?
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o?Setting up LVS run parameters?
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o?Displaying errors using the graphical user interface?
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o Locating LVS errors
Unit 3
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o Running layout versus schematic checks (continued)?
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o?Debugging LVS with multiple errors?
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o?Using the main debugging tools?
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o?Mismatched nets and mismatched devices?
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o?Shorts locator and opens locator?
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o?Malformed devices?
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o?Pins, parameters, and rewire tools
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o?Unguided debugger lab module?
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o?Running an electrical rules check (ERC)
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