Overview
In this workshop, you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design. The class explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length, and reusing functional pins for scan testing; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.
ObjectivesAt the end of this workshop the student should be able to:
- Define the test protocol for a design and customize the initialization sequence, if needed
- Perform DFT checks at both the RTL and gate levels
- State common design constructs that cause typical DFT violations
- Automatically correct certain DFT violations at the gate level using AutoFix
- Insert scan to achieve well-balanced top-level scan chains and other scan design requirements
- Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and place & route.
- Implement Rapid Scan Synthesis (RSS) in a top-down scan insertion flow achieving well-balanced scan chains
- Modify a bottom-up scan insertion script for full gate-level designs to use test models/ILMs with RSS and run it
- Preview top-level chain balance using test models/ILMs after block-level scan insertion and revise block-level scan architecture as needed to improve top-level scan chain balance.
- Modify a scan insertion script to include DFT-MAX Adaptive Scan compression
Audience Profile
Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million-gate SoCs, and export design files to ATPG and P&R tools
Prerequisites
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision, and with writing Synopsys Tcl scripts is useful, but not required.
Course 1.
- Introduction to Scan Testing
- DFT Compiler Flows
- DFT Compiler Setup
- Test Protocol
- DFT Design Rule Checks
2.
- DFT DRC GUI Debug
- DRC Fixing
- Top-Down Scan Insertion
3.
- Exporting Files
- High Capacity DFT Flows
- Multi-Mode DFT
- DFT MAX
Synopsys Tools Used
- DFT Compiler 2010.03-SP3
- Design Vision 2010.03-SP3
- Design Compiler 2010.03-SP3
- TetraMAX 2010.03-SP3
主站蜘蛛池模板：
MM1313亚洲精品无码久久|
麻豆亚洲AV永久无码精品久久|
久久影院午夜理论片无码|
精品久久久久久无码中文野结衣|
无码人妻丰满熟妇区BBBBXXXX|
亚洲av无码国产综合专区|
无码人妻少妇伦在线电影|
国产精品无码一区二区三级|
亚洲AV无码国产一区二区三区|
中文国产成人精品久久亚洲精品AⅤ无码精品
|
亚洲国产精品无码中文字|
无码国内精品人妻少妇|
免费无码一区二区|
精品无码AV一区二区三区不卡|
一级电影在线播放无码|
无码精品A∨在线观看免费|
东京无码熟妇人妻AV在线网址|
伊人久久大香线蕉无码|
无码人妻一区二区三区一|
亚洲AV永久无码精品一福利|
日韩人妻无码精品系列|
无码人妻精品丰满熟妇区|
少妇精品无码一区二区三区|
亚洲精品无码激情AV|
亚洲国产精品无码久久98|
亚洲av无码不卡|
综合无码一区二区三区|
日韩中文无码有码免费视频|
亚洲av片不卡无码久久|
无码一区二区三区老色鬼|
中文字幕无码第1页|
heyzo专区无码综合|
国产乱子伦精品免费无码专区|
亚洲中文无码卡通动漫野外|
少妇人妻无码专区视频|
无码国产精品一区二区免费vr|
亚洲日韩精品无码专区网址|
成人午夜精品无码区久久|
国产精品无码素人福利|
亚洲Av无码乱码在线znlu|
亚洲成a人无码av波多野按摩
|
